Demodulator for demodulating digital broadcast signals

ABSTRACT

To present a digital broadcast demodulator, in a demodulator of digital terrestrial wave broadcast for transmitting coded digital video and audio information in a packet form, capable of detecting packet synchronism stably and precisely, controlling the AGC, and processing the clock regeneration, in spite of inferior environments for receiving broadcast, such as deterioration of C/N of signal due to weak electric field, or strong ghost or multipath characteristic of terrestrial waves.

DETAILED DESCRIPTION OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to a digital broadcast demodulator fordemodulating a digital modulated signal modulated, for example, bymulti-value VSB modulation, in digital broadcast for digitaltransmission by coding video and audio information.

2. Prior Art

Recently, owing to the advancement in the digital compression technologyand digital modulation and demodulation technology, the televisionbroadcast is presented by using satellites and CATV. The video data iscoded by MPEG2, and the digital modulation system is realized by theQPSK method in satellite broadcast or QAM method in CATV. In the UnitedStates, the terrestrial digital broadcast (DTV) is scheduled from thefall of 1998, and the digital modulation 8VSB system by videocompression by MPEG2 is planned.

Referring to the drawing, a conventional example of receiving anddemodulating apparatus of digital terrestrial broadcast is explainedbelow.

FIG. 10 is a block diagram of a demodulator of terrestrial digitalbroadcast. Reference numeral 1 is an antenna for receiving an RF signal,2 is a tuner for selecting a channel, 3 is a SAW filter for limiting theband, 4 is an amplifier for amplifying a signal, 5 and 6 are mixers, 7is a phase shifter for delaying the phase by 90°, 8 is a voltagecontrolled oscillator (VCO), 9 and 10 are low pass filters, 11 is an AGCdetector for determining the average of signal amplitude, 12 is an A/Dconverter for converting an analog signal into a digital signal, 13 is aband pass filter, 14 is a square circuit, 15 is a band pass filter, 16is a phase detector for detecting a phase error, 17 is a loop filter, 18is a voltage controlled oscillator, 19 is a symbol judging circuit forjudging the value of symbol data, 20 is a data value of a knownsynchronous signal, 21 is a synchronous signal detecting circuit fordetecting the synchronous signal in the reception data, and 22 is awaveform equalizer.

In thus constituted demodulator, the operation is explained below. An RFmodulated wave signal received by the antenna 1 is put into the tuner 2,and an arbitrary channel is selected. In the tuner 2, the selectedsignal is controlled of gain and is issued as an intermediate frequency(IF). The IF output from the tuner 2 is limited in band in the frequencycharacteristic determined in the SAW filter 3, and is put into theamplifier 4.

In the amplifier 4, by a control signal from an AGC detector explainedlater, the signal level is controlled, and is supplied into mixers 5, 6.The IF signal supplied in the mixers 5, 6 is multiplied by the localfrequency signal from the voltage controlled oscillator 8 (VCO) toundergo quadrature detection. After quadrature detection, base bandsignals of I, Q signals are supplied into the LPF 9 and LPF 10,individually.

Herein, the mixer 6 delivers a beat signal generated by the differencebetween the carrier frequency and the frequency signal from the VCO, andit is put into the LPF 9, and is supplied into the VCO 8 as frequencyerror signal. A reproduction carrier from the VCO 8 is put into themixer 5, and a carrier delayed in phase by 90° is supplied into themixer 6 through the 90-degree phase shifter 7. By constituting a PLL bythe system of the mixer 6, LPF 9, VCO 8 and 90-degree phase shifter 7,the local signal equal to the carrier frequency of the receptionmodulated wave can be oscillated by the VCO 8.

The base band signal supplied into the LPF 10 is limited to a desiredfrequency characteristic, and is supplied into the A/D converter 12 andthe AGC detector 11. In the AGC detector 11, detecting the envelope ofthe entered base band signal, an AGC control signal is generated. As theAGC control signal is fed back to the amplifier 4 and tuner 2 andcontrolled, the AGC operation is carried out.

On the other hand, the base band signal supplied into the A/D converter12 is converted into a digital signal, and is supplied into ademodulation processing unit and the waveform equalizer in a laterstage. The digital data delivered from the A/D converter 12 is put intothe BPF 13, and a frequency component Fs/2 of the symbol frequency (Fs)of data speed is extracted.

Being supplied into the square circuit 14, the frequency component ofFs/2 is squared, and is put into the BPF 15. In the BPF 15, a frequencycomponent Fs equal to the symbol speed is extracted, and put into thephase comparator 16. In the phase comparator 16, a phase error from thesymbol frequency is detected, and supplied into the loop filter 17.

In the loop filter 17, the phase error signal is integrated, andsupplied as control signal of VCO 18. By constituting the feedback loopto the BPF (FS/2) 13, square circuit 14, BPF (FS) 15, phase comparator16, loop filter 17, and VCO 18, the clock is regenerated.

Further, the digital data is supplied into the symbol judging circuit19, and the value of the received symbol data is judged, and suppliedinto the synchronous signal detecting circuit 21. In the synchronoussignal detecting circuit, comparing with the symbol data value of thesynchronous reference signal from the known data circuit 20 ofsynchronous signal, the synchronous signal of packet data is detected.

Thus, in order to demodulate the digital terrestrial broadcast 8VSB orthe like, important steps are synchronous signal detection processing oftransmission packet data, AGC processing for controlling signalamplitude, and clock regeneration for extracting and regenerating clockcomponent from transmission data.

[Problems that the Invention is to Solve]

However, in the event of occurrence of inferior environments forreceiving broadcast, such as characteristic ghost and multipath ofdigital terrestrial broadcast, and same channel interference by NTSC orother analog broadcast, it is extremely difficult to detect thesynchronism, operate the AGC or regenerated the clock precisely in suchsynchronous detection processing by precisely judging the data value ofthe symbol, AGC processing by determining the average of detected baseband signals, or clock regeneration processing of extracting thefrequency components in the transmission data. Accordingly, in order toraise the precision, it was required to process by heightening thesampling frequency, or compose the filter by a considerably largecircuit.

[Means of Solving the Problems]

To solve the above problems, the digital broadcast demodulator of theinvention is characterized by comprising means for detecting andestablishing the synchronous signal in reception data by processing onlythe code bit (MSB) of the reception data, means for operating andprocessing the data only for the period of synchronous signal, means forregenerating a clock by detecting the phase error from the differentialvalue, and means for performing AGC by comparing the data value of thedetected synchronous signal and the reference of the known synchronoussignal.

EMBODIMENTS OF THE INVENTION

Referring now to the drawings, preferred embodiments of the inventionare described below. First in FIG. 1, the digital broadcast demodulatorof the invention is described, particularly about the schematicconstitution of the digital broadcast demodulator of digital terrestrialbroadcast VSB modulation system, and then the embodiments correspondingto the claims of the invention are specifically described.

Reference numeral 1 is an antenna for receiving an RF signal, 2 is atuner for selecting a channel, 3 is a SAW filter for limiting the band,4 is an amplifier for amplifying a signal, 5 and 6 are mixers, 7 is aphase shifter for delaying the phase by 90°, 8 is a voltage controlledoscillator VCO, 9 and 10 are low pass filters, 11 is an AGC detector fordetermining the average of signal amplitude, 12 is an A/D converter forconverting an analog signal into a digital signal, and 22 is a waveformequalizer.

Output digital data of the A/D converter 12 is put into a synchronous(sync) code pattern detecting circuit 101, and synchronous pattern isdetected by processing the code bit. The output of the synchronous codepattern detecting circuit 101 is supplied into a detection protectioncounter circuit 103, a segment synchronism detection establishingcircuit 104.

The output of the segment synchronism detection establishing circuit 104is supplied into a symbol number counter 102, and the counting result ofthe number of symbols in one packet is fed back into a detectionprotection counter 103 and a segment sync detection establishing circuit104. On the basis of the fed-back information, a segment start signal109 showing the position of segment synchronous signal in the packet,and a segment establishment signal 110 showing the detectionestablishment of the segment synchronous signal are issued.

The segment synchronism establishment signal 110 is put into a switchcircuit 111 to become a switch signal for changing over a control signalfrom an AGC error detecting circuit 106 mentioned below and a controlsignal from the AGC detector circuit 11.

The digital data of the A/D converter output is supplied into the clockphase error detecting circuit 105, and is fed together with the signalfrom the sync pattern detecting circuit 101 and the segment startsignal, and a clock phase error of data is issued as clock regenerationcontrol signal to a terminal 108. This clock regeneration control signalis put into a D/A converter 112, and is converted into an analog signal,which is fed into the LPF 113. The control signal integrated in the LPF113 is put into the VCO 18 to control its oscillation frequency. Afeedback loop is composed in the flow of the VCO 18, A/D converter 12,clock phase error detecting circuit 105, D/A converter 112, and LPF 113.

Further, the digital data of the A/D converter output is put also intothe AGC error detecting circuit 106, and issued into the terminal 107 asan AGC control signal. The AGC control signal is put into the D/Aconverter 114, and is converted into an analog signal, and is suppliedinto the LPF 113. The AGC control signal integrated in the LPF 113 issupplied into the switch circuit 111.

The AGC control signal supplied into the switch circuit 111 is changedover, by the segment establishment signal, between the control signalfrom the analog AGC detector 11 and the AGC control signal detected bydigital processing. The AGC control signal as output from the switchcircuit 111 is put into the amplifier 4 and tuner 2, and the amplitudeof the input signal is controlled.

In thus constituted digital broadcast demodulator, specific embodimentscorresponding to the claims are described below.

Embodiment 1

FIG. 2 shows a block diagram of embodiment 1 corresponding to claims 1,2, 3 of the invention. This embodiment relates to a digital broadcastdemodulator used in an apparatus for receiving digital broadcast bytransmitting coded digital video and audio information in packet form,in which, particularly in digital VSB transmission system, the circuitis constituted to process the code bit (MSB) of reception transportpacket data, and the synchronous signal in the reception data isestablished. In this constitution, even in an inferior radio wavecondition for receiving broadcast, such as ghost, multipath, or samechannel interference of NTSC, the synchronous signal in the packet canbe detected and established precisely and securely.

Referring now to FIG. 2, the operation is described below. In thedemodulator of the invention, the base band signal after quadraturedetection is put into the A/D converter 12, and the clock regenerationhas been already locked. Of the output digital data from the A/Dconverter 12, the code bit (MSB) is supplied into the sync patterndetecting circuit 101. Herein, the data structure of packet of VSBdigital terrestrial broadcast is shown in FIG. 5 and FIG. 6. Thetransmission frame shown in FIG. 5 is composed of 832 symbols in onepacket, and the segment sync signal is inserted by the portion of foursymbols only from the beginning.

In every 313 packets (segments), field sync signals #1, #2 are inserted.FIG. 6 shows the field sync signal. At the beginning of the packet, asegment sync signal of four symbols, and a specific number of PN codesare composed. The segment sync signal is a mapping signal in the valuesof +5, −5, −5, +5 as shown in FIG. 6. This signal value is the knowndata, and is inserted at the beginning of all packets as shown in FIG.5.

In the sync pattern detecting circuit 101, the code bit (MSB) of allreception data is processed, and +, −, −, +as code pattern of segmentsync signal are detected. When processing the signal by the complementof 2, the codes of the segment synchronous signal are −, +, +, −.

When processing the code bits only, even in the presence of strongghost, multipath interference or NTSC same channel interferencecharacteristic of digital terrestrial broadcast, the reception datareceives considerably effects of impedance, and deterioration occurs,but the code bit information is extremely strong against effects ofinterference even in the inferior reception wave situation, so that thesynchronous pattern of the segment sync signal can be detected stably.

When detecting the sync pattern for four symbols in all reception datain the sync pattern detecting circuit 101, simultaneously, signal sdetis issued to the detection protection counter 103 and segment syncdetection establishing circuit 104. When counting 832 symbols in onepacket, a signal Co is issued to the detection protection counter 103and segment sync detection establishing circuit 104.

In the segment sync detection establishing circuit 104, sync patterndetection signal sdet, symbol number count-up signal Co, and signal Shldfrom detection protection counter 103 are supplied, if there is samepattern as the segment sync code pattern in all reception data, it isjudged which pattern is the true segment sync signal.

In the operation, an output signal Lo is issued until the signal Co tobe issued when reaching the symbol number count 832 of the packet, andthe segment synchronous code pattern detection signal sdet are enteredsimultaneously.

Usually, in the reception data, there are many code pattern data same asthe segment synchronous code pattern, but the symbol number counter 102counts up to 832 which is the number of symbols in one packet when thesame code pattern detection signal sdet as the segment sync is entered,but when a sync code pattern is detected on the way, the signal Lo isissued from the segment sync detection establishing circuit 104, and thesymbol number counter 102 is reset. Thus, the counting operation isrepeated until the signal sdet is entered simultaneously with the outputof signal Co of count-up of symbol number 832 of one packet. That is, inthe case of a true segment sync signal, when counting of 832 is over,simultaneously, there is a segment sync signal of next packet, and thesignal sdet and signal Co are simultaneously entered.

The output signal Co of the symbol number counter 102 and the outputsignal sdet of the sync pattern detecting circuit 101 are also suppliedinto the detection protection counter 103. The detection protectioncounter 103 counts the number of times of simultaneous input of signalsdet and signal Co, and detects and establishes as the true segment syncsignal in the reception data while Sdet and Co are enteredsimultaneously for a predetermined number of times. When detecting andestablishing the segment sync signal in the reception data, the segmentestablished signal Shld is issued.

Once the segment is established, if signal sdet and signal Co are notentered simultaneously, the segment establishment is not canceledimmediately, but when making mistakes by a specified number of times ormore, the establishment of segment sync detection is canceled.

Thus, the constitution of this embodiment comprises the circuit 101 fordetecting the known synchronous signal code pattern by processing onlythe code bit (MSB) of the reception data, symbol number counter 102 forcounting the number of symbols in one packet, segment sync detectionestablishing circuit 104, and detection protection counter circuit 103,and therefore even in an inferior radio wave condition for receivingbroadcast such as strong ghost or multipath characteristic of digitalbroadcast, same channel interference of NTSC broadcast, low C/N, andothers, the synchronous signal can be detected and established stably,and decoding can be processed stably.

Embodiment 2

FIG. 3 shows a block diagram of embodiment 2 corresponding to claims 4,5, 6 of the invention. This embodiment relates to a digital broadcastdemodulator used in an apparatus for receiving digital broadcast bytransmitting coded digital video and audio information in packet form,in which, particularly in digital VSB transmission system, the clockphase error of reception data is obtained by calculating the differenceof N-th and N+1-th (N>1) packet synchronous signals of reception data,and the clock is regenerated stably even in an inferior radio wavereception circumstance.

Referring now to FIG. 3, the operation is described below. The brokenline block 116 corresponds to the segment sync detection establishingcircuit block of embodiment 1, and it issues the segment syncestablishing signal in the reception data and segment start signalshowing the position of the segment sync signal in the packet. Theoperation of block 116 is same as explained in embodiment 1, and isomitted.

The reception digital data issued from an A/D converter 12 is put into aclock phase error detecting circuit 201. The segment sync detectionestablishing circuit block 116 also feeds the signal sdet showing theposition of the same data as the code pattern of the sync signal in thepacket data and the signal Segst showing the position of segment signalin the packet data.

FIG. 9 shows a block diagram of clock phase error detecting circuit 201.The digital data from the A/D converter 12 is put into a subtractingcircuit 202 through a latch 203, and is further put into the subtractingcircuit 202 through a latch 204. In the subtracting circuit 202, theN-th input and the N+1-th input are subtracted, and the subtractionvalue is put into a latch circuit 207. In the latch circuit 207, thedata is latched by the signal sdet of code pattern detection of segmentsynchronous signal, and issued into a latch circuit 208. The signal sdetis adjusted in time so as to latch the subtraction value at the timingafter subtraction operation of the second and third segment sync signalsof reception data by the latch circuit 205. In the latch circuit 208, bylatching by the signal Segst showing the position of the segment syncsignal to be sent out after detecting and establishing the segment syncsignal, it is sent out as clock phase error signal Pherr. The signalSegst is also adjusted in time to the timing to be latched by the latchcircuit 208, by the subtracted values of the second and third segmentsync signals in the latch circuit 206.

FIG. 7 shows sample points of segment sync signal unit. The samplepoints are a, b, c, d when the oscillation frequency of the VCO iscompletely matched in phase with the clock of the reception data. Thedata values are smooth values because the band is limited by filteringprocessing in the preceding stage. Herein, supposing the N-th data to bethe second data value b, by subtraction from the N+1-th data value c,b−c is processed.

As shown in FIG. 7, the subtraction processing is to determine theinclination of sample point values b and c. Herein, when the clock ofthe reception data and the phase of the frequency signal oscillated bythe VCO 18 are synchronized completely, the value of b−c is 0. If thefrequency or phase is deviated, as indicated by broken line in FIG. 7,it is like b′−c′, and the clock phase error signal Pherr is determinedby subtraction process. Feedback control is executed so that this clockphase error signal Pherr may be close to 0. As shown in FIG. 1, theclock phase error is fed into the D/A 112 to be converted into an analogsignal, and is supplied into the LPF 113. The clock phase errorconverted into analog signal is integrated in the LPF 113, and issupplied into the VCO 18 as clock phase control signal. In the VCO 18,the oscillation frequency signal is controlled on the basis of the clockphase control signal, and it is synchronized with the clock signal ofthe reception data by the PLL.

Incidentally, according the invention as set forth in claim 7, whenturning on the power or changing over the channels, until the segmentsync signal of the packet is detected and established, it is intended tofinish the clock regeneration quickly by feeding back the differentialvalue of all data that should be originally of the same level matchedbetween the sync signal and code pattern in the packet data,continuously to the VCO 18 as clock phase error.

In this embodiment, from the signal Segst showing the position of thesynchronous signal of the data being sent out in packet form and thesignal sdet showing the sync signal in the packet data and the codepattern are the same data, the N-th and N+1-th sync signals of thepacket data are processed by subtraction, and the clock phase errorsignal Pherr is determined, and the clock regeneration process isexecuted.

In this method, even in an inferior radio wave condition for receivingdigital broadcast, the clock regeneration is realized stably in a verysimple and inexpensive circuit constitution.

Embodiment 3

FIG. 4 shows a block diagram of embodiment 3 corresponding to claims 8,9 of the invention. This embodiment presents an apparatus, that is, adigital broadcast demodulator for receiving digital broadcast bytransmitting coded digital video and audio information in packet form,in which, particularly in digital VSB transmission system, thesynchronous signal is detected in the received packet data, and from thesynchronism detection establishment signal and the signal showing theposition of the synchronous signal in the packet, the difference betweenthe data value of synchronous signal and the reference value iscalculated, and thereby AGC is realized.

Referring now to FIG. 4, the operation is described below. The brokenline block 116 corresponds to the segment sync detection establishingcircuit block shown in embodiment 1, and it issues the segment syncestablishing signal Shld showing establishment of detection of segmentsync signal in the reception data and segment start signal showing theposition of the segment synchronous signal in the packet. The operationof block 116 is same as explained in embodiment 1, and is omitted. Thedigital data output from an A/D converter 12 is put into an AGC errordetecting circuit 301.

Also, from the segment sync detection establishing block 116, the signalShld showing detection and establishment of the segment sync signal inthe packet data and the signal Segst showing the position of sync signalare also entered.

FIG. 8 shows segment sync signals added to the beginning of packet data.The segment sync signal is mapped in the values of ±5 as shown in FIG.8. Since these are known values, at the reception side, the data valuescorresponding to ±5 may be possessed as reference values. From thesignal Segst showing the position of the segment sync signal in thepacket, the data values of four symbols from the beginning of thesegment sync are subtracted from the reference value. As shown in FIG.8, when the reception data is entered as indicated by broken line, thedifference from the reference value is as indicated by d at the +side,and d′ at the −side. Feedback control is executed so that thedifferences d, d′ from the reference value may be closer to 0.

This is to show a case in which reception data larger than the referencevalue of segment synchronous signal is entered, but when data smallerthan the reference value is entered, by subtracting after absolute valueprocessing so that the code may not be inverted by subtraction processto increase the differential value, the AGC error signal Gerr is issuedas AGC control signal. The AGC control signal is put into the D/Aconverter 114 as shown in FIG. 1, and is supplied into the LPF 115. TheAGC control signal integrated by the LPF 115 is fed into the amplifier 4and tuner 2 through the switch circuit 111, and by feedback control, theamplitude of the reception data is controlled to realize AGC.

According to claim 10 of the invention, when turning on the power orchanging over the channels, until the segment sync signal in the packetdata is detected and established, it is intended to change over the AGCcontrol signal between the control signal of detecting the amplitudeerror from the envelope of the analog signal and the control signal ofdetecting the amplitude error from the sync level by digital processing,by supplying the segment establishing signal Shld issued from theterminal 110 shown in FIG. 1 into the SW circuit 111. When the receptiondata is entered, until the segment sync signal of the packet is detectedand established, the AGC control in the analog processing unit in thepreceding stage is applied by priority, and after detecting andestablishing the segment sync signal in the packet, the error signalfrom digital processing for detecting the amplitude error from thesynchronous signal is fed back, and the AGC is done efficiently.

In this embodiment 3, from the signal Segst showing the position ofsynchronous signal of data sent in packet form, and the signal Shldshowing the detection and establishment of the sync signal, bysubtraction processing of the segment synchronous signal of receptiondata and reference value of segment signal, the amplitude error signalGerr is determined, and D/A converted, and integrated by LPF, and putinto the analog amplifier and tuner through the SW circuit 111, there bycontrolling the amplitude and realizing AGC. In this method, even in aninferior radio wave condition for receiving digital broadcast, such asghost and multipath, the AGC is realized stably in a very inexpensivecircuit constitution, and the AGC control is realized stably.

[Effects of the Invention]

As described herein, the invention, relating to digital terrestrialbroadcast of packet data or the like, comprises sync pattern detectingmeans for processing code bits of reception data, symbol number countermeans, sync detection protection counter means, and sync detectionestablishing means, in which the true synchronous signal pattern isestablished and detected, and therefore even in an inferior radio wavecondition, such as strong ghost and multipath interferencecharacteristic of digital terrestrial broadcast, the synchronous signalin the packet can be established and detected stably in a veryinexpensive circuit constitution.

Also comprising subtracting means of reception data, by determining theinclination between synchronous signals, from the same code patterndetection signal as the sync signal and the signal showing the positionof sync signal in the packet, the clock phase error of reception data isdetected, and fed back to the VCO for controlling, and therefore even inan inferior radio wave condition, such as strong ghost and multipathinterference characteristic of digital terrestrial broadcast, low C/N,and others, the clock can be regenerated stably and precisely in a veryinexpensive circuit constitution.

Further, by subtracting the synchronous signal of reception data andknown reference value from the signal showing the position ofsynchronous signal in the reception packet data and the signal detectingand establishing the synchronous signal in the packet data, theamplitude error is determined, and fed back to the analog amplifiercircuit and tuner for controlling, so that precise AGC is realized evenin an inferior radio wave environment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a general block diagram of a digital broadcast demodulator ofthe invention.

FIG. 2 is a block diagram of digital broadcast demodulator in embodiment1 of the invention.

FIG. 3 is a block diagram of digital broadcast demodulator in embodiment2 of the invention.

FIG. 4 is a block diagram of digital broadcast demodulator in embodiment3 of the invention.

FIG. 5 is a data frame diagram of digital terrestrial broadcast VSBmodulation system.

FIG. 6 is a field sync signal diagram of digital terrestrial broadcastVSB modulation system.

FIG. 7 is a sample waveform diagram of segment synchronous signalexplaining embodiment 2 of the invention.

FIG. 8 is a waveform diagram of segment sync signal explainingembodiment 3 of the invention.

FIG. 9 is a block diagram of clock phase error detecting circuit of theinvention.

FIG. 10 is a block diagram showing a constitution of a digital broadcastdemodulator in a prior art.

REFERENCE NUMERALS

-   1 Reception antenna-   2 Digital broadcast tuner-   3 SAW filter-   4 Analog amplifier for amplifying signal-   5, 6 Mixer-   7 90-degree phase shifter-   8, 18 VCO (voltage controlled oscillator)-   9, 10 LPF (low pass filter)-   11 AGC detector for detecting signal envelope-   12 A/D converter-   13 Band pass filter for passing frequency component of ½ of symbol    speed-   14 Square circuit-   15 Band pass filter for passing frequency component of symbol speed    Fs-   16 Phase detector for detecting phase error-   17 Loop filter-   19 Symbol judging device-   20 Synchronous signal reference data-   21 Synchronous signal detector-   22 Waveform equalizer-   101 Sync pattern detecting circuit-   102 Symbol number counter-   103 Detection protection counter-   104 Segment sync detection establishing circuit-   105 Clock phase error detecting circuit-   106 AGC error detecting circuit-   107 AGC control signal terminal-   108 Clock regeneration control signal terminal-   109 Segment start signal (Segst) terminal-   110 Segment establishing (Shld) terminal-   112, 114 D/A converter-   113, 115 LPF-   116 Segment sync detection establishing block

1. A digital broadcast demodulator, being an apparatus for receivingdigital broadcast by transmitting digital video and audio informationcoded by digital VSB modulation system in packet form, comprising: acircuit for establishing a synchronous signal in reception data based ona polarity of the most significant bit (MSB) of the reception transportpacket data, wherein the circuit for establishing the synchronous signalin reception data comprises: a synchronous code pattern detectingcircuit for detecting the segment synchronous code pattern from the mostsignificant bit signal of the reception packet data, a symbol numbercounter circuit for counting the number of symbol data in the receptionpacket data, a synchronism detection establishing circuit for judgingthe true segment synchronous code pattern by obtaining the segmentsynchronous code pattern from said synchronous code pattern detectingcircuit when said symbol number counter circuit finishes counting of aspecified number, and a synchronism detection protection counter circuitfor detecting and establishing the segment synchronous signal in thereception data from the output of said synchronous code patterndetecting circuit and count-up of specified number of said symbol numbercounter circuit.
 2. A digital broadcast demodulator of claim 1, whereinthe most significant bit signal of the reception packet data isprocessed so as to issue a signal showing the start position of thesynchronous signal in the data and a signal of detecting andestablishing the synchronous signal.
 3. A digital broadcast demodulatorof claim 1, being an apparatus for receiving digital broadcast bytransmitting digital video and audio information coded by digital VSBmodulation system in packet form, wherein a differential value ofsynchronous signals of reception packet data is determined so as todetect a clock phase error of transmission data, and a clock signal isregenerated by phase control on the basis of said clock phase error,said digital broadcast demodulator further comprising a clock phaseerror detecting circuit for issuing a clock phase error of transmissiondata by determining the difference of the N-th and N+1-th (N>1)synchronous signals which should be of same level by nature, from thecode pattern detection signal of synchronous signal and signal showingposition of synchronous signal.
 4. A digital broadcast demodulator,being an apparatus for receiving digital broadcast by transmittingdigital video and audio information coded by digital VSB modulationsystem in packet form, wherein a differential value of synchronoussignals of reception packet data, which should be of the same level bynature, is determined so as to detect a clock phase error oftransmission data, and a clock signal is regenerated by phase control onthe basis of said clock phase error, said digital broadcast demodulatorfurther comprising: (a) a subtracting circuit for subtracting the N-thinput from the N+1 th input of all reception data, (b) a circuit foroutputting the subtraction input value obtained in step (a) only for thedata coinciding with the code pattern of segment synchronous signal, and(c) a circuit for outputting said subtraction input value obtained instep (b) as a clock phase error signal only for the data positioned atthe segment synchronous signal, wherein only the phase errors of asecond symbol and a third symbol or a first symbol and a fourth symbolof said segment synchronous signal are outputted as said clock phaseerror.
 5. A digital broadcast demodulator of claim 1, being an apparatusfor receiving digital broadcast by transmitting digital video and audioinformation coded by digital VSB modulation system in packet form,wherein a synchronous signal in the received packet data is detected,the difference between the detected data value of the synchronous signaland a predetermined reference value is determined, and automatic gaincontrol is performed on the basis of this difference, said digitalbroadcast demodulator further comprising an AGC error detecting circuitfor detecting a specific position of synchronous signal from the signalshowing detection and establishment of synchronous signal in thereception data and the signal showing position of synchronous signal,and issuing the error of the synchronous signal at this specificposition and the reference value as a control signal.
 6. A digitalbroadcast demodulator according to claim 1, wherein said polarity of themost significant bit (MSB) of the reception transport packet data iseither positive or negative.